1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device capable of electrically writing and erasing data and retaining its data when power is removed.
2. Description of the Background Art
Nonvolatile semiconductor devices are mounted in systems as memory devices capable of retaining data in a nonvolatile manner at portable terminals to comply with the recent development in digital communication networks using portable information terminals such as portable telephones, internets and the like. Among such nonvolatile semiconductor memory devices, for example, there is a flash memory which is capable of collectively and electrically erasing stored data by a prescribed number of bits and electrically writing data.
FIG. 16 is a schematic diagram showing a cross sectional structure of a memory cell transistor of a so-called NOR flash memory, among such flash memories, in conjunction with the first erasing operation.
Referring to FIG. 16, a memory cell of the flash memory is provided with a multilayer gate disposed on a P well 10 formed in a main surface of the semiconductor substrate. The multilayer gate is provided with a gate oxide film 13, a floating gate 14 of polycrystalline silicon or the like, an insulating film 15 generally called an ONO film having three layers of an oxide film, nitride film, and oxide film for preventing leakage, and a control gate 16 formed of polycrystalline silicon or the like. In vicinity of the multilayer gate on P well 10, an N type source region 12a and drain region 12b are formed in a self-aligning manner.
In the following description, assume that a source voltage Vs, a drain voltage Vd, a control voltage Vcg, and a well potential Vw are respectively applied to the source region, drain region, control gate and P well 10.
In the erasing operation of the memory cell of the flash memory shown in FIG. 16, a high voltage Vpp (up to 10V) obtained by boosting an external power supply voltage is applied as source voltage Vs to a source of the memory cell. The drain is brought into a floating state. A ground potential is used as potential Vw of P well 10. Thus, electrons accumulated in floating gate 14 can be extracted and swept into the side of the source.
FIG. 17 is a diagram showing a cross sectional structure of a memory cell array in which such NOR type flash memories are arranged.
In the structure shown in FIG. 17, bit lines are hierarchically divided into a main bit line MBL and sub bit lines SBL1 and SBL2 respectively connected to main bit line MBL via select transistors Trs1 and Trs2, in order to make a data writing unit as small as possible. More specifically, data is only written to the memory cell block connected to sub bit line SBL1 (or SBL2) selected by select transistor Trs.
As in FIG. 16, if the erasing operation is performed by extracting electrons from the source, a back gate of the memory cell transistor, or P well 10, can be shared by blocks to be erased and select transistors.
On the other hand, in an erasing method of an NOR type flash memory, a high voltage is applied to the back gate of the memory cell, or P well 10, so that electrons in floating gate 14 is extracted and swept into the side of P well 10 and a threshold voltage Vth of the memory cell transistor is decreased.
FIG. 18 is a schematic diagram shown in conjunction with a second erasing method of such an NOR type flash memory.
As shown in FIG. 18, in the second erasing method, source potential Vs and drain potential Vd of the memory cell transistor are both equal to a boosted potential Vpp, and a potential of the P well is also equal to boosted potential Vpp.
A potential of the control gate is for example equal to a ground potential.
FIG. 19 is a cross sectional view shown in conjunction with a structure of a memory cell array when data is erased by extracting electrons from such a P well 10 (a back gate).
In the method shown in conjunction with FIG. 18, as the erasing operation is performed by extracting electrons toward the side of P well 10, P wells 10.1 and 10.2 must be separated by an N well 8 for every data writing unit (a memory block). In addition, also for select transistors Trs1 and Trs2 which select memory blocks for a writing operation, a P well 10.0 including select transistors Trs1 and Trs2 must be separated from P wells 10.1 and 10.2 of the writing units, i.e., memory blocks.
As described above, although the second erasing method has an advantage over the first erasing method in terms of reliability and the like, the wells for the memory blocks as writing units and the well for select gates Trs1 and Tr2 must be separated. Thus, a region required for separation of wells increases, whereby a memory cell area as a whole disadvantageously increases.